Although electrical subcircuit instance parameterization is allowed and works fine when generating simulation files for SPICE, it is ignored in LVS. The LVS system implicitly assumes that a cell and its instances are precisely similar, that an instance of a cell is in all respects defined by the master cell of the instance. Instance parameterization is therefor not recognized (but parameters defined in the cell itself are fine).
One has similar issues with parameterized physical cells. With parameterized cells, a unique master is created for each unique set of instantiation parameters used in the design. The template cell ``instance'' is not really an instance of the template cell, but is actually an instance of a master created for a particular parameter set.
Within LVS, each physical template master would correspond to an electrical master, and likewise there would be correspondence between instances. Presently, all of this must be configured manually. Work is ongoing to fully support parameterization through SPICE, physical and electrical cells, and LVS, in a transparent manner.