For compatibility with other simulators, the keyword ``.elseif'' is accepted as an alias for ``.elif''.
The WRspice input file syntax supports conditional blocks, through use of these directives. The expression can involve constants, parameter names from a .param line included in the file, or vectors and shell variables defined before the file is read. It does not understand variables implicitly set by inclusion in the .options line, or parameters set in .subckt lines or references. The scope for these constructs is always global, meaning that they apply to lines of text in the file without regard to .subckt block boundaries.
The construct def(paramname) can be used in the expression, where it is replaced by 1 or 0 if paramname is defined or not. Thus, one can define parameters that have not been previously defined with
If the single expression is nonzero, or the two expressions yield the same result, the lines following .if up to the matching .elif, .else or .endif are read, and if an .else block follows, those lines to the matching .endif are discarded. If the single expression if zero or the two expressions do not match, the lines following .if to the matching .elif, .else or .endif are discarded, and if a .else line follows, the lines following .else to .endif are retained. These blocks can be nested. The action is similar to the C preprocessor.
This filtering is performed early in the parsing of the file, so that the .if, etc. lines can enclose script lines, Verilog blocks, etc., and not simply circuit lines. The lines not in scope are never saved in memory.
The predefined read-only WRSPICE_RELEASE parameter can be used in conjunction with the .if conditionals to select WRspice-specific lines in input files.
.param WRSPICE_RELEASE=0 $ This is ignored by WRspice
(lines for HSPICE or whatever)